Improving Circuit Testability by Clock Control
نویسندگان
چکیده
T h e testabili ty of a sequential circuit can be i m proved by controlling the clocks of individual storage elements during testing. W e propose several clock control strategies derived f r o m a n analysis of the circuit, i t s S-graph structure, and i ts funct ion. Through examples we show how the number of clocks aflects the circuit’s testability. It i s shown that if certain flip-flops (FFs) are scanned (or otherwise initialized), the remaining FFs can be controlled and initialized t o a n y arbitrary state using the clock control. W e derive a controllability graph and use it t o assign clocks t o FFs and t o schedule the clocks t o set t he FFs t o a n arbitrary state during tes t . Our analysis of sequential benchmark circui ts indicates tha t this could be a n attractive scheme for combining partial scan with clock control.
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